View THM72V2010AG_4623970.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TOSHIBA
THM72V2010AG/ATG-60/70
PRELIMINARY
2,097,152 WORDS X 72 BIT DYNAMIC RAM MODULE
Description The THM72V2010AG/ATG is a 2,097,152 words by 72 bits dynamic RAM module which assembled 9 pcs of TC51V17800ANJ/ANT on the printed circuit board. This module is optimized for application to the systems which are required high density and large capacity such as main memory of the computers and as image memory systems, and to the others which are requested compact size. Features * 2,097,152 words by 72 bits organization * Fast access time and cycle time * Single power supply of 3.3V5% * Low Power - 4,095mW MAX. Operating - (THMxxxxxx-60) - 3,470mW MAX. Operating - (THMxxxxxx-70) - 50.4mW MAX. Standby * Read-Modify-Write, CAS before RAS refresh, RAS-only refresh, Hidden refresh, and Fast Page Mode capability * All inputs and outputs TTL compatible * 2,048 refresh cycles/32ms * Package: 168pin Gold Contact THM72V2010AG-x SOJ type THM72V2010ATG-x TSOP type Key Parameters
-60 tRAC tAA RAS Access Time Column Address Access Time CAS Access Time Cycle Time Fast Page Mode Cycle Time 60ns -70 PD0 70ns PD1 PD2 35ns 40ns PD3 PD4 20ns 25ns PD5 PD6 PD7 40ns 45ns ID0 ID1 -60 "H" "L" "L" "H" "L" "H" "H" "L" VSS VSS -70 "H" "L" "L" "H" "L" "L" "H" "L" VSS VSS
tCAC tRC tPC
110ns 130ns
Note "H": High Level (buffered) "L": Low Level (buffered)
1. This technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-export, directly or indirectly, in contravention of the U.S. Export Administration Regulations is strictly prohibited. 2. LIFE SUPPORT POLICY Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate officer of Toshiba America, Inc. Life support systems are either systems intended for surgical implant in the body or systems which sustain life. A critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness. 3. The information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. All information in this data book is subject to change without prior notice. Furthermore, Toshiba cannot assume responsibility for the use of any license under the patent rights of Toshiba or any third parties.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
1
THM72V2010AG/ATG-60/70 Pin Name
B0, A0 ~ 9, A10R DQ0 ~ 71 RAS0, 2 CAS0, 4 WE0, 2 OE0, 2 VCC VSS PD0 ~ 7 ID0, 1 NC Address Inputs Data Input/Outputs Row Address Strobe Column Address Strobe Write Enable Output Enable Power (+3.3V) Ground Presence Detect Pin ID bit No Connection
Standard DRAM
DM16050295
Pin Connection (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
VCC
102
VCC
35
A4 A6 A8 NC VCC NC NC VSS OE2
119 120 121 123 124 125 126 127 128
A5 A7 A9 NC NC VCC NC B0 VSS NC NC NC NC PDE VCC NC NC
52 DQ18 136 DQ54 69 DQ28 153 DQ64 53 DQ19 137 DQ55 70 DQ29 154 DQ65 54 VSS 138 VSS 71 DQ30 155 DQ66 VCC 157 VCC 55 DQ20 139 DQ56 72 DQ31 156 DQ67 56 DQ21 140 DQ57 73 57 DQ22 141 DQ58 74 DQ32 158 DQ68 58 DQ23 142 DQ59 75 DQ33 159 DQ69 59 61 62 63 64 VCC NC NC NC NC 143 145 146 147 148 VCC NC NC NC NC 76 DQ34 160 DQ70 78 79 80 81 VSS PD0 PD2 PD4 PD6 ID0 VCC 162 163 164 165 166 167 168 VSS PD1 PD3 PD5 PD7 ID1 VCC 60 DQ24 144 DQ60 77 DQ35 161 DQ71
DQ14 103 DQ50 36 DQ15 104 DQ51 37 DQ17 106 DQ53 39 VSS NC NC VCC WE0 NC OE0 VSS A0 A2 107 108 109 110 111 113 115 116 117 118 VSS NC NC VCC NC NC NC NC NC VSS A1 A3 40 41 42 43 44
DQ16 105 DQ52 38 A10R 122
CAS0 112 RAS0 114
45 RAS2 129 46 CAS4 130 47 48 49 50 51 NC WE2 VCC NC NC 131 132 133 134 135
65 DQ25 149 DQ61 82 66 DQ26 150 DQ62 83 67 DQ27 151 DQ63 84 68 VSS 152 VSS
2
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Block Diagram
Standard DRAM
THM72V2010AG/ATG-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
3
THM72V2010AG/ATG-60/70 Absolute Maximum Ratings
SYMBOL VIN VOUT VCC TOPR TSTG PD IOUT Input Voltage Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current ITEM
Standard DRAM
DM16050295
RATING -0.3 ~ VCC + 0.3 -0.3 ~ VCC + 0.3 -0.5 ~ 4.6 0 ~ 70 -55 ~ 125 3.9 50
UNIT V V V C C W mA
NOTE 1 1 1 1 1 1 1
Recommended DC Operating Conditions (Ta = 0 ~ 70C)
SYMBOL VCC VIH VIL Supply Voltage Input High Voltage Input Low Voltage PARAMETER MIN 3.13 2.2 -0.3** TYP 3.3 MAX 3.47 VCC + 0.3* 0.8 UNIT V V V NOTE 2 2 2
*VCC + 1.2V at pulse width 20ns (pulse width is measured at VCC). **-1.2V at pulse width 20ns (pulse width is measured at VSS).
4
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295
Standard DRAM
THM72V2010AG/ATG-60/70
DC Electrical Characteristics (VCC = 3.3V 5%, Ta = 0 ~ 70C)
SYMBOL |CC1 PARAMETER OPERATING CURRENT Average Power Supply Operating Current (RAS, CS, Address Cycling: tRC=tRC MIN.) STANDBY CURRENT Power Supply Standby Current (RAS=CAS=VIH) RAS ONLY REFRESH CURRENT Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS=VIH: tRC=tRC MIN.) FAST PAGE MODE CURRENT Average Power Supply Current, Fast Page Mode (RAS=VIL, CAS, Address Cycling: tPC=tPC MIN.) STANDBY CURRENT Power Supply Standby Current (RAS=CAS=VCC-0.2V) CAS BEFORE RAS REFRESH CURRENT Average Power Supply Current, CAS Before RAS Mode (RAS, CAS Cycling: tRC=tRC MIN.) INPUT LEAKAGE CURRENT Input Leakage Current, any input (0VVINVCC, All Other Pins Not Under Test=0V) OUTPUT LEAKAGE CURRENT (DOUT is disabled, (0VVOUTVCC) OUTPUT LEVEL Output "H" Level Voltage (IOUT= -2mA) OUTPUT LEVEL Output "L" Level Voltage (IOUT=2mA) THMxxxxxx-60 THMxxxxxx-70 THMxxxxxx-60 THMxxxxxx-70 THMxxxxxx-60 THMxxxxxx-70 THMxxxxxx-60 THMxxxxxx-70 MIN -10 MAX 1180 1000 19 1180 1000 685 595 14.5 1180 1000 10 mA 3, 5 mA mA 3, 5 mA UNIT NOTE 3, 4 5
|CC2
mA
|CC3
|CC4
3, 4 5
|CC5
mA
|CC6
|I (L) |O (L) VOH VOL
A A V V
-10 2.4 -
10 0.4
Capacitance (VCC = 3.3V5%, f = 1MHz, Ta = 0 ~ 70C)
SYMBOL CI1 CI2 CI3 CI4 CI5 CI6 CDQ PARAMETER Input Capacitance (B0, A0 ~ A9, A10R) Input Capacitance (WE0, 2) Input Capacitance (RAS0, 2) Input Capacitance (CAS0, 4) Input Capacitance (OE0, 2) Input Capacitance (PDE) I/O Capacitance (DQ0 ~ 71) MIN MAX 13 10 33 10 10 13 30
PF
UNIT
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
5
THM72V2010AG/ATG-60/70
Standard DRAM
DM16050295
Electrical Characteristics and Recommended AC Operating Conditions (VCC = 3.3V5%, Ta = 0 ~ 70C) (Notes 6,7,8)
THMxxxxxx-60 SYMBOL tRC tRMW tPC tPRMW tRAC tCAC tAA tCPA tCLZ tOFF tT tRP tRAS tRASP tRSH tRHCP tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH PARAMETER Random Read or Write Cycle Time Read-Modify-Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read-Modify-Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge CAS to Output in Low-Z Output Buffer Turn-off Delay Transition Time (Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time from CAS Precharge (Fast Page Mode) CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time CAS Precharge Time Row Address Set-Up Time Row Address Hold Time Column Address Set-Up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-Up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Hold Time MIN 110 165 40 95 0 0 3 40 60 60 20 40 60 15 20 15 10 10 0 10 0 10 35 0 0 10 10 MAX 60 20 35 40 20 50 10,000 200,000 10,000 40 25 THMxxxxxx-70 MIN 130 190 45 105 0 0 3 50 70 70 25 45 70 20 20 15 10 10 0 10 0 15 40 0 0 10 15 MAX 70 25 40 45 20 50 10,000 200,000 10,000 45 30 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 14 15 9, 14, 15 9, 14 9, 15 9 9 10 8 NOTES
6
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295
Standard DRAM
THM72V2010AG/ATG-60/70
Electrical Characteristics and Recommended AC Operating Conditions (Cont)
THMxxxxxx-60 SYMBOL tWP tRWL tCWL tDS tDH tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tROH tOEA tOED tOLZ tOEZ tOEH tODS tWTS tWTH tWRP tWRH tPD tPDOFF PARAMETER Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data Set-Up Time Data Hold Time Refresh Period Write Command Set-Up Time CAS to WE Delay Time RAS to WE Delay Time Column Address to WE Delay Time CAS Precharge to WE Delay Time CAS Set-Up Time (CAS before RAS Cycle) CAS Hold Time (CAS before RAS Cycle) RAS to CAS Precharge Time CAS Precharge Time (CAS before RAS Counter Test Cycle) RAS Hold Time Referenced to OE OE Access Time OE to Data Delay OE to Output in Low-Z Output buffer turn off Delay Time from OE OE Command Hold Time Output Disable Set-Up Time Write Command Set-Up Time (Test Mode In) Write Command Hold Time (Test Mode In) WE to RAS Precharge Time (CAS before RAS Cycle) WE to RAS Hold Time (CAS before RAS Cycle) PDE to Presence Detect Data in Low-Z Presence Detect Data turn off Delay Time from PDE MIN 10 20 15 0 15 0 50 90 65 70 10 10 5 20 15 20 0 0 15 0 15 10 15 10 1 MAX 32 20 20 10 THMxxxxxx-70 MIN 15 25 20 0 20 0 55 100 70 75 10 15 5 30 15 20 0 0 15 0 15 10 15 10 1 MAX 32 25 20 10 UNIT ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 13 13 13 13 13 12 12 NOTES
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
7
THM72V2010AG/ATG-60/70
Standard DRAM
DM16050295
Electrical Characteristics and Recommended AC Operating Conditions (VCC = 3.3V5%, Ta = 0 ~ 70C) (Notes 6,7,8)
THMxxxxxx-60 SYMBOL tRC tPC tRAC tCAC tAA tCPA tRAS tRASP tRSH tCSH tRHCP tCAS tRAL PARAMETER MIN Random Read or Write Cycle Time Fast Page Mode Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Hold Time CAS Precharge to RAS Hold CAS Pulse Width Column Address to RAS Lead 115 45 65 65 25 65 45 20 40 MAX 65 25 40 45 10,000 200,000 10,000 MIN 135 50 75 75 30 75 50 25 45 MAX 75 30 45 50 10,000 200,000 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9, 14, 15 9, 14 9, 15 9 THMxxxxxx-70 UNIT NOTES
8
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
Standard DRAM
THM72V2010AG/ATG-60/70
14. 15.
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. All voltages are referenced to VSS. ICC1, ICC3, ICC4, ICC6 depend on cycle rate. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed one or less while RAS=VIL. In case of ICC4, it can be changed once or less during a fast page mode cycle (tPC). An initial pause of 500s is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. When the internal refresh counter is used, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required. AC measurements assume tT=5ns. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. This parameter is measured with a load equivalent to 100pF and at VOH=2.0V (IOUT= -2mA), VOL=2.0V (IOUT=2mA). tOFF (max.) and tOEZ (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-Modify-Write cycles. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (min.), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) through the entire cycle; If tRWDtRWD (min.), tCWDtCWD (min.), tAWDtAWD (min.) and tCPWDtCPWD (min.) (Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. Operation within the tRCD (max.) limit insures that tRAC can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA.27
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
9
THM72V2010AG/ATG-60/70 Timing Waveforms Read Cycle
Standard DRAM
DM16050295
10
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Write Cycle (Early Write)
Standard DRAM
THM72V2010AG/ATG-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
11
THM72V2010AG/ATG-60/70 Write Cycle (OE Controlled Write)
Standard DRAM
DM16050295
12
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Read-Modify-Write Cycle
Standard DRAM
THM72V2010AG/ATG-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
13
THM72V2010AG/ATG-60/70 Fast Page Mode Read Cycle
Standard DRAM
DM16050295
14
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Fast Page Mode Write Cycle (Early Write)
Standard DRAM
THM72V2010AG/ATG-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
15
THM72V2010AG/ATG-60/70 Fast Page Mode Read-Modify-Write Cycle
Standard DRAM
DM16050295
16
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 RAS Only Refresh Cycle
Standard DRAM
THM72V2010AG/ATG-60/70
CAS Before RAS Refresh Cycle
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
17
THM72V2010AG/ATG-60/70 Hidden Refresh Cycle (Read)
Standard DRAM
DM16050295
18
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Hidden Refresh Cycle (Write)
Standard DRAM
THM72V2010AG/ATG-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
19
THM72V2010AG/ATG-60/70 CAS Before RAS Refresh Counter Test Cycle
Standard DRAM
DM16050295
20
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 WE, CAS Before RAS Refresh Cycle
Standard DRAM
THM72V2010AG/ATG-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
21
THM72V2010AG/ATG-60/70 Presence Detect Data Read Cycle
Standard DRAM
DM16050295
22
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Read Cycle in the Test Mode
Standard DRAM
THM72V2010AG/ATG-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
23
THM72V2010AG/ATG-60/70 Write Cycle (Early Write) in the Test Mode
Standard DRAM
DM16050295
24
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Fast Page Mode Read Cycle in the Test Mode
Standard DRAM
THM72V2010AG/ATG-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
25
THM72V2010AG/ATG-60/70 Fast Page Mode Write Cycle in the Test Mode
Standard DRAM
DM16050295
26
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295
Standard DRAM
THM72V2010AG/ATG-60/70
Test Mode The TC51V17800ANJ/ANT is the RAM organized as 2,097,152 words by 8 bits, it is internally organized as 1,048,576 words by 16 bits. In "Test Mode", data are written into 16 sectors in parallel by using only I/O1. A9C is not used. If, upon reading, 16 bits are equal (all "1"'s or "0"'s), the I/O8 pin indicates a "1". If they were not equal, the I/O8 pin would indicate a "0". Other I/O pins (I/O1 ~ 7) always indicate a "1" a during test mode read cycle. Figure 1 shows the block diagram of TC51V17800ANJ/ANT. In "Test Mode", the 2Mx8 DRAM can be tested as if it were a 1Mx16 DRAM. "WE, CAS Before RAS Refresh Cycle" puts the device into "Test Mode", and "CAS Before RAS Refresh Cycle" or "RAS Only Refresh Cycle" puts it back into "Normal Mode". In the Test Mode, "WE, CAS Before RAS Refresh Cycle" performs the refresh operation with the internal refresh address counter. The "Test Mode" function reduces test times (1/2 in case of N test pattern).
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
27
THM72V2010AG/ATG-60/70 Block Diagram in the Test Mode
Standard DRAM
DM16050295
28
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY
DM16050295 Outline Drawing THM72V2010AG
Standard DRAM
THM72V2010AG/ATG-60/70
Unit in mm
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
29
THM72V2010AG/ATG-60/70 Outline Drawing THM72V2010ATG
Standard DRAM
DM16050295
Unit in mm
30
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY

▲Up To Search▲

Price & Availability of THM72V2010AG

	To Download THM72V2010AG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .